vtr-verilog-to-routing
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Published
20 hours ago •
verilog-to-routing
verilog-to-routing
Unexpected attribute 'tileable' found on node 'layout'
this is the command I ran:
~/vtr-verilog-to-routing/vpr/vpr k4_N4_tileable_40nm.xml xor_cipher.blif --clock_modeling route
vpr_arch is from https://github.com/lnis-uofu/OpenFPGA/blob/master/openfpga_flow/vpr_arch/k4_N4_tileable_40nm.xml
it gives error:
VPR FPGA Placement and Routing.
Version: 8.1.0-dev+f669015f3
Revision: v8.0.0-6941-gf669015f3
Compiled: 2023-02-10T16:13:42
Compiler: GNU 9.4.0 on Linux-5.15.0-58-generic x86_64
Build Info: release IPO VTR_ASSERT_LEVEL=2
University of Toronto
verilogtorouting.org
[email protected]
This is free open source code under MIT license.
VPR was run with the following command-line:
/home/pc-1/vtr-verilog-to-routing/vpr/vpr k4_N4_tileable_130nm.xml xor_cipher.blif --clock_modeling route
Architecture file: k4_N4_tileable_130nm.xml
Circuit name: xor_cipher
# Loading Architecture Description
Warning 1: Model 'io' input port 'outpad' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 2: Model 'io' output port 'inpad' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
# Loading Architecture Description took 0.00 seconds (max_rss 16.3 MiB, delta_rss +1.5 MiB)
Error 1: k4_N4_tileable_130nm.xml:65 Unexpected attribute 'tileable' found on node 'layout'.
The entire flow of VPR took 0.00 seconds (max_rss 16.3 MiB)
not sure why it worked on openfpga but not on vpr itself
