[ExportVerilog] Initial statement needs begin/end for single declaration

[uenoku]

Input:

hw.module private @Foo() -> (){
    sv.initial {
      %param_x = sv.localparam : i42 { value = 11: i42 }
    }
}

$ circt-opt -export-verilog produces:

module Foo();
  initial     
    localparam [41:0] param_x = 42'd11; 

endmodule

At least Verilator and Yosys produce a syntax error. When I added "begin" and "end" around initial statement, it parses.

  initial begin 
    localparam [41:0] param_x = 42'd11;
  end

[youngar]

There is a similar test in the verilog parser suite: https://chipsalliance.github.io/sv-tests-results/?v=verilator+9.2.1+initial