Sean Cross
Sean Cross
The `riscv32imac-unknown-xous-elf` target is a new Tier 3 platform. This platform uses standard Os-less `-none-` toolchains, as Rust provides all standard libraries and IPC functionality.
On Windows, the `cc` crate takes great pains to synthesize a usable environment by replicating MSVC in how it generates an environment. However, the environment is incomplete, and does not...
If a Markdown file is in a different directory and includes images, the paths are not preserved when the file is inserted into the source document. For example: ```rst .....
The page indicates that a release is available at https://fosse.co/latest.zip, however this is simply a blank HTML page with a Google tracker in it. There is no binary available at...
It would be nice to be able to delegate interrupts to happen in user mode. This should be as simple as setting a bit in the `SIDELEG` register, which would...
If you're using the DebugPlugin to debug a core, and it issues a `WFI` with no interrupts enabled, then that core will freeze and be unrecoverable with the DebugPlugin. The...
VexRiscv implements a simple MMU. This MMU is effective, but nonstandard, and requires extended instructions to do refilling. Would it be possible to give a simple example of how to...
The MulPlugin, DivPlugin, and MulDivIterativePlugin all require that `withWriteBackStage = true` and `withMemoryStage = true`. This can make it difficult to shrink the core, especially since the MulPlugin ought to...
After a discussion with @Dolu1990 , it was revealed that 50% of the gate count of a minimal VexRiscv is the register file, which is 32x32-bits. That's many registers. The...
Somewhat related to #27 -- if you include this crate in a project, it won't build on any other platforms. This can be worked around by adding a Cargo-level conditional....