Wilson Snyder

I'm worried about the runtime cost here. Usually the practice is to wait for reset, which should clear all user signals, then clear all toggle counters. Does that solve most...

Usually there is still some init-done point, and even if not, I dont understand how this change prevents false coverage during first reset.

My point is from the verification engineer's standpoint, proving something has toggled is related to reset - you can only ensure functionality of a toggle outside reset, so they should...

Sorry I was not clear it is only the first init that is not part of any test resets does the clear. Later resets are covered intentionally, so that you...

A methodology should, for tests using any sort of coverage (not just toggle) ,in pseudo-code, do roughly: ``` initial start clocks do reset sequence couple cycles assert reset run few...

>We want to implement a solution that will not require the user to modify the code, so that they can switch easily from another simulator to Verilato That's fair, implement...

Closing this pull as it is stale, it will still serve as a reference. The base issue still needs to be fixed; the comments suggested a different approach.

Running Verilator with e.g. identical Verilog code and a user C++ file that changes will only re-make that C++ file (it will not regenerate C++). This will require the intermediate...

Yes, I'd suggest the patch. We can consider a patch to add an remove-intermediate build option once you've proven it works well, if you need it.

BTW if you aren't already doing so, you can also use an action to build verilator into a artifact and restore it, so you don't need to rebuild every time....