Wilson Snyder
Wilson Snyder
Self checking test. ``` `define stop $stop `define checkh(gotv,expv) do if ((gotv) !== (expv)) begin $write("%%Error: %s:%0d: got='h%x exp='h%x\n", `__FILE__,`__LINE__, (gotv), (expv)); `stop; end while(0); module t; bit stmt2 =...
CC @kbieganski
I tried the second half, V3Timing alone, and that broke a lot, I assume it isn't necessary part of the tix. The first one breaks many tests with >%Warning: t/t_timing_fork_join.v:55:...
Closer but still causes bunch of test unsupported fallout, beyond the `#0` warnings. I'm leaving this for a while, if someone wants to pick it up. ``` diff --git a/src/V3Fork.cpp...
@kbieganski As to `soft` I don't see an obvious reason that shouldn't parse, I can look at that if you'd like.
Looked at the `size` problem, I believe that the shift operation needs to be adjusted to always be within bounds of the bit vector, probably with some condition to return...
While inconsistent, 3 of 5 simulators surveyed print enum.name when %s is used. When I/someone gets to this issue we should likewise support that.
The example passes on current master, there have been many SIDEEFFECT improvements but it's also possible some other change is now hiding the problem. If your larger test case still...
Hi Andreas! There's already `verilog-auto-inst-template-numbers` we could add `'none` to that. Might you be willing to make a pull for this including a test?