Wilson Snyder
Wilson Snyder
Great! @kozdra might you be able to advise as to how @steven-bellock can get started?
@YilouWang perhaps you'd be interested in adding this (& see also #4706).
That sounds roughly right. If you could please make a pull it would be appreciated, also please check against the verilator_ext_tests as these warnings tend to have false positives until...
Confirmed the code passes on all simulators I tried, as noted in the comments this is legal in SystemVerilog but not IEEE 1364. As general policy Verilator doesn't plan at...
V3Width which checks interface functions currently doesn't really do much with modports, so this is something that will need to wait for the backlog before I can get to it....
Yes, though Verilator doesn't complain which is probably another bug.
Do other simulators likewise capture 0->1 and 1->0 separately? At my site we just look for e.g. 10 transitions, and then know both 0->1 and 1->0 are well covered. This...
Fair points. Note Verilator captures numbers separately for the instances, it's the annotation that might combine them.
Anyhow I'm ok taking the change but would like the refactoring mentioned to reclaim performance, it can be part of this patch or a separate pre-pull (which has the advantage...
@kozdra? @WisniewskiP if he doesn't have that in flight, perhaps you'd consider a pull request to implement it, or at least a pull to add tests for the feature to...