wisxxx

FPGA IP Licensing

9

What are the licensing or royalty arrangements for the FPGA intellectual property? There appear to be six IP cores from NetTimeLogic in use.

FPGA pin assignments for production version

2

What are the pin assignments for the "Version: 0x8003 (Production Version)" FPGA? They aren't in "Readme_Production.pdf".

Updated FPGA

2

"Time-Card/SOM/FPGA/TimeCard_FPGA.png" shows an extra GNSS receiver (UART and PPS connections) as well as an UART in the upper left that is not labelled. These don't appear on the SOM connector...

beta-v1 schematics issues

2

- What is "RV-3049-C3" (U10A and U10B, p.5,A3)? - The labels on the off-page connectors on p. 6 seem to be interspersed with CR (0x0d) characters. The corresponding net names...

MAC_USB_PWR

3

MAC_USB_PWR goes to connector P1B-B8 and thence to FPGA pin V8, IO_L14P_T2_SRCC_13, per the AC7100 schematics. This is curious, since USB power is +5V and there is no +5 going...

Why +3.3V regulator when +3.3V available on PCIe connector?

2

The +3.3V step-down regulator on p. 2, C3 has a max current rating of 2 A, for 6.6 W power. Since the PCIe connector allows for up to 9.9 W...

PCIe Bracket V3 dimensions

5

The vertical hole centers are referenced to the top surface of the short bend section at the upper end of the bracket. This position, being on the outside of the...

BOM and schematic errata

3

**BOM** - item 41 (DS3231 RTC) shows "U5" as ref des. schematic shows "U3A" - item 40 (1x3 header) does not have corresponding jumpers - item 29 (IC REG BUCK...

Production Timecard: bad termination on FPGA JTAG with USB

2

Ref. schematic R4006-G0001-03-SC-REV02.pdf If using the USB interface (FT432, sht. 24), the FPGA JTAG signals are double-terminated by resistors shown at sht. 24, zone B11: >  and sht. 10,...