FPGA IP Licensing

[wisxxx]

What are the licensing or royalty arrangements for the FPGA intellectual property?

There appear to be six IP cores from NetTimeLogic in use.

[ahmadexp]

The current license with NetTimeLogic allows the use of the bin file. Alternatively we are working on a version without the proprietary IPs. Hopefully coming soon. @thschaub can add more to that.

[thschaub]

Exactly, it is allowed to use the IP cores as implemented in the bin file. If you have adaptation proposals which have a common interest we can also check if it make sense to adapt something as part of this binary license.

There are five NetTimeLogic IP Cores as part of the binary license included (PPS Slave, PPS Master, TOD Slave, Adjustable Clock and Signal Timestamper). The "UART to AXI" and "Static config" are included in the licensing of any other IP Core. Additionally, there are IP Cores included from Xilinx (AXI UART, AXI Memory Mapped to PCI Express, AXI IIC, AXI GPIO etc.) which are under their end user license agreement: https://www.xilinx.com/content/dam/xilinx/licenses/ip/end-user-license-agreement.pdf

Currently we are checking different options for a version without the proprietary IP.

[geerlingguy]

@AlphaBetaPhi - Was there any other update on this or is this issue closed as other options won't be investigated at this time?

[AlphaBetaPhi]

Hi @geerlingguy, we are still investigating this. I'll label appropriately.

[thschaub]

There will be soon an update about the open source FPGA version.

https://www.opencompute.org/wiki/Time_Appliances_Project on Mar-23, 2022, there will be a call about Open Time Card FPGA

[thschaub]

Hi @geerlingguy, hi @wisxxx a first version of the base system (without TOD Slave and PPS Slave) is released: https://github.com/opencomputeproject/Time-Appliance-Project/tree/master/Time-Card/FPGA/Open-Source

[wisxxx]

Thanks. I see the pinout in

…/Implementation/Xilinx/TimeCard/Constraints/PinoutConstraint.xdc

Good info.

From: Thomas Schaub @.> Sent: Friday, June 3, 2022 5:20 AM To: opencomputeproject/Time-Appliance-Project @.> Cc: wisxxx @.>; Mention @.> Subject: Re: [opencomputeproject/Time-Appliance-Project] FPGA IP Licensing (#17)

Hi @geerlingguy https://github.com/geerlingguy , hi @wisxxx https://github.com/wisxxx a first version of the base system (without TOD Slave and PPS Slave) is released: https://github.com/opencomputeproject/Time-Appliance-Project/tree/master/Time-Card/FPGA/Open-Source

[wisxxx]

The pinout appears to show that the PCie interface is reduced to one lane. Am I reading it correctly?

[thschaub]

The pinout appears to show that the PCie interface is reduced to one lane. Am I reading it correctly?

Not really related to this topic. If you build the open source FPGA project you could see the configuration of the PCIe memory mapped bridge in Vivado. And yes it's only one lane.

[thschaub]

Full Open-Source Project including video tutorials available: https://github.com/opencomputeproject/Time-Appliance-Project/tree/master/Time-Card/FPGA/