wisxxx

It appears the the analog frequency control input to the MAC-SA5x oscillator is connected to a digital I/O pin in the FPGA. Is this intended? In 'Timingcard_SCHEMATICS_BETA_V1.pdf", p. 6,A3 and...

It would be electrically compatible (by PCIe definition), but the performance decrease would likely affect system operation. It may be that there is an application where reduced accuracy, latency, and...

**UPDATE**: A check of the 3D model setup shows that this is a non- or very low risk issue. Careful management of the Z offsets of the STEP models reduces...

What is the reference feature for the connector centerline dimension? If it is the top surface of the ear, then the extension line is drawn incorrectly. 

What is the bracket material thickness? Is it the PCIe CEM standard 20 ga (0.86 +/- 0.08 mm, 34 +/- 3 mils)? Ref: PCI Express Card Electromechanical Specification, Revision 4.0,...

To quantify the connector to I/O bracket cutout misalignment: 1.1 mm (43 mils), assuming the 6.83 mm dimension in the drawing is from the top of the mounting ear attaching...

Can't answer: I haven't received any direct comments on any item, nor have I seen an updated schematic.

Thanks. I see the pinout in …/Implementation/Xilinx/TimeCard/Constraints/PinoutConstraint.xdc Good info. From: Thomas Schaub ***@***.***> Sent: Friday, June 3, 2022 5:20 AM To: opencomputeproject/Time-Appliance-Project ***@***.***> Cc: wisxxx ***@***.***>; Mention ***@***.***> Subject: Re:...

The pinout appears to show that the PCie interface is reduced to one lane. Am I reading it correctly?

Nonetheless, it appears that the power input to the MAC USB interface is incorrectly connected to an I/O pin on the FPGA, as shown on the currently available schematics. Can...