veryl
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veryl-lang
Veryl: A Modern Hardware Description Language
Bumps [parol_runtime](https://github.com/jsinger67/parol) from 0.21.0 to 0.22.0. Release notes Sourced from parol_runtime's releases. parol_runtime + v0.21.0 parol v0.28.0 + parol-ls v0.18.0 What's Changed Brand new support for LALR(1) grammar types Don't...
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Bumps [parol](https://github.com/jsinger67/parol) from 0.28.0 to 0.29.0. Release notes Sourced from parol's releases. parol_runtime + v0.21.0 parol v0.28.0 + parol-ls v0.18.0 What's Changed Brand new support for LALR(1) grammar types Don't...
I think it would be nice generics parameters have their default value like `parameter`. ```systemverilog function foo:: -> logic { } ```
Some keyword of SystemVerilog can be used as identifier in Veryl. They will cause syntax error of transpiled SystemVerilog code. So they should be checked by Veryl compiler.
This feature is inspired from * https://github.com/Jacajack/hdl/ * https://www.reddit.com/r/FPGA/comments/1cltdak/comment/l3aop3y/?utm_source=share&utm_medium=web3x&utm_name=web3xcss&utm_term=1&utm_content=share_button By introducing clock type, clock domain can be represented in RTL and CDC (clock domain crossing) check can be achived. As...
refs: https://github.com/veryl-lang/veryl/issues/622#issuecomment-2030848796 To connect clock/reset signals having different types, we need to introduce clock/reset type cast. When an operand and a cast type have different polarity, an inverter logic will...
refs: https://github.com/veryl-lang/veryl/issues/622#issuecomment-2030848796 To prevent clock/reset type mismatch, we need to check type mismatch on clocl/reset port connections. ```systemverilog module ModA ( i_clk: input clock_posedge, i_rst_n: input reset_async_low ) {} module...
Some Veryl's keyword can be used as identifier in SystemVerilog. So instantiating a SystemVerilog module may cause syntax error. ```systemverilog module ModuleA ( i_clk: input clock, i_rst: input reset, )...
I noticed that Veryl compiler accepts using a period instead of double colon to access the variant of an `enum`, which it shouldn't. ``` package foobar_pkg { enum FooBar: logic...
