Clock domain annotation

[dalance]

This feature is inspired from

• https://github.com/Jacajack/hdl/
• https://www.reddit.com/r/FPGA/comments/1cltdak/comment/l3aop3y/?utm_source=share&utm_medium=web3x&utm_name=web3xcss&utm_term=1&utm_content=share_button

By introducing clock type, clock domain can be represented in RTL and CDC (clock domain crossing) check can be achived. As the same as Rust's Lifetime Elision, I think it is good that clock domain is infered by compiler in almost all cases, explicit annotation is needed in some special cases.

I think the annotation should be placed at module port declaration because port is public API. This results that Veryl compiler can check CDC violation without cross-module analysis. Additionally more useful module documentation can be generated.

For example,

// all port belongs the same clock domain which is based on `i_clk` implicitly
module ModuleA (
    i_clk : input  clock,
    i_data: input  logic,
    o_data: output logic,
) {}

// if there are some clocks, explicit clock domain annotation is needed
module ModuleA (
    i_clk_a : 'a input  clock,
    i_data_a: 'a input  logic,
    o_data_a: 'a output logic,
    i_clk_b : 'b input  clock,
    i_data_b: 'b input  logic,
    o_data_b: 'b output logic,
) {}

// show 2clocks belong the same clock domain
module ModuleA (
    i_clk   : 'a input  clock,
    i_clk_x2: 'a input  clock,
    i_data  : input  logic,
    o_data  : output logic,
) {}

// show feed through pass independent from implicit clock domain baseed on `i_clk`
module ModuleA (
    i_clk    : input  clock,
    i_data   : input  logic,
    o_data   : output logic,
    i_through: 'a input logic,
    o_through: 'a output logic,
) {}

The annotation for point of cross domain crossing will be required too. But I don't have no idea now.