[Feature] clock/reset port connection check

[taichi-ishitani]

refs: https://github.com/veryl-lang/veryl/issues/622#issuecomment-2030848796

To prevent clock/reset type mismatch, we need to check type mismatch on clocl/reset port connections.

module ModA (
  i_clk:   input clock_posedge,
  i_rst_n: input reset_async_low
) {}

module ModB (
  i_clk: input clock,
  i_rst: input reset
){
  inst u_moda: ModA (
    i_clk:   i_clk, // these connection include type mismatch
    i_rst_n: i_rst  // so Veryl should report an error.
  );
}