vtr-verilog-to-routing

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Allow pin offsets (x, y, layer) in connection block specifications to build the rr-graph

2

Currently vpr allows the pins connecting blocks -> routing channel segments to be on various sides and locations within or on the perimeter of a block. Xilinx 7-series (and perhaps...

vaughnbetz

Docker image doesn't support vpr graphics

1

I haven't personally reproduced this, but I have a report from Dong that the vpr docker image doesn't enable the graphics. #### Expected Behaviour We should have all the dependencies...

vaughnbetz

vpr graphics only show final results (post-routing)

1

#### Expected Behaviour VPR should be able to view the placement and show its evolution (if the user wishes to see it), and let users even specify manual moves to...

vaughnbetz

`DESTDIR=/opt/vtr cmake --build ./ --target install` writes content in `/opt/vtr/tmp/vtr/build/*/yosys`

2

The following procedure: https://github.com/hdl/containers/blob/442f15fd80ee5d2935602880c59b6b8ff2077f22/debian-bullseye/vtr.dockerfile#L47-L52 ```bash git clone https://github.com/verilog-to-routing/vtr-verilog-to-routing.git /tmp/vtr mkdir -p /tmp/vtr/build cd /tmp/vtr/build cmake -G "Ninja" -DCMAKE_INSTALL_PREFIX="/usr/local" .. cmake --build ./ DESTDIR=/opt/vtr cmake --build ./ --target install ``` Writes...

umarcor

can't pack adder

1

we hope to implement adder using the hard adder instead of luts, however , the packer rise an error. #### Expected Behaviour our adder should be packed without any error...

narutozxp

Odin II and blifexplorer compiler warnings (should fix)

1

#### Expected Behaviour We should have no compiler warnings. #### Current Behaviour Odin II and blifexplorer and have compiler warnings. Some are: /usr/include/c++/11/type_traits:2960:14: warning: noexcept-expression evaluates to ‘false’ because of...

vaughnbetz

Using Parmys For Xilinx-Like Architectures

11

I tried to implement `stereovision0.v` on `simple-7series.xml`. I ran this command: `run_vtr_flow.py stereovision0.v simple-7series.xml` and got this error message: `simple-7series/stereovision0 Error: Executable yosys failed full command: /usr/bin/env time -v /home/mohagh18/vtr-verilog-to-routing/build/bin/yosys...

amin1377

From PR 2187: I think we should move the #ifndef NO_GRAPHICS here and the #endif after "} else" and before the "if" in line 1472 so that the manual_move_enabled will...

vaughnbetz

CVE-2007-4559 Patch

2

# Patching CVE-2007-4559 Hi, we are security researchers from the Advanced Research Center at [Trellix](https://www.trellix.com). We have began a campaign to patch a widespread bug named CVE-2007-4559. CVE-2007-4559 is a...

TrellixVulnTeam

Update Dockerfile

1

#### Description #### Related Issue #### Motivation and Context #### How Has This Been Tested? #### Types of changes - [ ] Bug fix (change which fixes an issue) -...

KevinLi2596