vtr-verilog-to-routing
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Published
20 hours ago •
verilog-to-routing
verilog-to-routing
Remove has_path_to_sink
The router has a function that was added for the initial 3D routing (from OPINs) that checks some high-level architecture variables and decides whether or not to expand a node. We shouldn't do this; the lookahead should (and according to @amin1377, does) instead highly cost nodes that are on a layer such that they don't have good paths to the target sink.
Hence this function is bad -- we should figure out the routing path solely from the rr-graph, not high-level architecture variables.
Expected Behaviour
We should be able to delete this function and still achieve good 3D routing runtime.
Current Behaviour
Things are working for the OPIN crossing case, but not the 3D switch block case. Maybe this code is involved. In any case, it is messy.
Possible Solution
Delete this function and test.
