vtr-verilog-to-routing
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Published
20 hours ago •
verilog-to-routing
verilog-to-routing
Test rr-graph write out and read in with a 3D architecture.
We should have a test for this, as we have some new tags (layers) and we also are autocreating a wire segment type for 3D switch blocks. We should have a test for that code path; it can be a very small device.
