riscv-mini
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Simple RISC-V 3-stage Pipeline in Chisel
There is no documentation on how the test hex files are generated. There could be a script to generate/update the hex files from the [`riscv-tests`](https://github.com/riscv-software-src/riscv-tests) repository.
Current `riscv-mini` implements RV32I of the User-level ISA Version 2.0 and the Machine-level ISA of the Privileged Architecture Version 1.7. This requires the users to build and install RISC-V tools...
Resolves #29. Still WIP: - [X] Update CSR implementation to match latest spec - [X] Unify hex files for Scala and verilator tests - [X] Modify the magic memory model...
I'm trying to generate either a Tile.fir or Tile.mlir file in the generated-src directory after running the make command. However, I'm facing an issue. Here's what I've done so far:...
In the nasti.scala file, the IO of the module NastiArbiter miss IO wrap
The way that strobe writes are implemented in `TileTester.scala` is broken. As it is now, it creates a `Wire` 70 bits long and writes junk data to the testing memory....
in the version chiselVersion = "5.0.0" chiseltestVersion = "5.0.2" version riscvmini: the code in datapath ``` ` val load = MuxLookup(ld_type, io.dcache.resp.bits.data.zext)( Seq( LD_LH -> lshift(15, 0).asSInt, LD_LB -> lshift(7,...
By the way,where can I get trainning about chisel develop for AXI, DMA,SRAM ,etc. Thanks
When one branch inst tries to jump to a misaligned address, such as: ```asm jal x1, 2 // misaligned beq x1,x2, 2 // misaligned but not trigger a exception ```...
```asm Addr Instruction Hex 00000200 addi x1, x1, 4 00408093 00000204 sw x0, 2(x0) 00002123 00000208 sh x1, 32(x2) 02111023 0000020c addi x1, x1, 4 00408093 ``` If run the...