riscv-mini
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Branch Instruction misaligned can't trigger exception
When one branch inst tries to jump to a misaligned address, such as:
jal x1, 2 // misaligned
beq x1,x2, 2 // misaligned but not trigger a exception
I find in the source code decode unit that only JAL and JARL is "PC_ALU" type insts:
JAL -> List(PC_ALU, A_PC, B_IMM, IMM_J, ALU_ADD , BR_XXX, Y, ST_XXX, LD_XXX, WB_PC4, Y, CSR.N, N),
JALR -> List(PC_ALU, A_RS1, B_IMM, IMM_I, ALU_ADD , BR_XXX, Y, ST_XXX, LD_XXX, WB_PC4, Y, CSR.N, N),
And in Datapath.scala, Line 167:
pc_check := io.ctrl.pc_sel === PC_ALU
I think it should be change to
pc_check := (io.ctrl.pc_sel === PC_ALU) || (brCond.io.taken)
And then the Branch Instruction misaligned can be triggered