UC Berkeley Architecture Research
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34
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UC Berkeley Architecture Research
chipyard
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598
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An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
gemmini
692
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144
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Berkeley's Spatial Array Generator
riscv-mini
504
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100
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Simple RISC-V 3-stage Pipeline in Chisel
chiseltest
207
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70
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The batteries-included testing and formal verification library for Chisel-based RTL designs.