chisel-tutorial
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ucb-bar
chisel tutorial exercises and answers
Hi, I think there is an issue in this tutorial in the line "val read_port1 = UInt(32.W)". Should it be "val read_port1 = Wire(UInt(32.W))"? Because UInt is a bare Chisel...
Following the steps [here](https://github.com/ucb-bar/chisel-tutorial/wiki/the-basics) At the "Generating Verilog" step when I run `./run-examples.sh GCD --backend-name verilator` command, I get an error like so: ``` `D --backend-name verilator [process_args] java_version =...
sbt problem
Hello, I am facing an error while I'm trying to sbt run: [error] (compile:compile) sbt.InvalidComponent: Could not find required component 'compiler-interface-src' Any ideas anyone? Thanks.
I think the synchronous memory description needs some rework. As far as I understand the synchronous memory has changed from Chisel 2 to 3 that the read address is already...
eg. https://github.com/ucb-bar/chisel-tutorial/wiki/Basic%20Types%20and%20Operations ```scala class FullAdder extends Module { val io = IO(new Bundle { val a = UInt(INPUT, 1) val b = UInt(INPUT, 1) val cin = UInt(INPUT, 1) val...
The problems/solutions are great. Is there any way to generate vcd files for added usefulness? There is some mention in the older documentation but this does not seem relevant for...
The code passes the test: ``` class RealGCDInput extends Bundle { val a = UInt(16.W) val b = UInt(16.W) } class RealGCD extends Module { val io = IO(new Bundle...
Section 5.1 of tutorial describes `Fill()`, `>>` and ` y ; wz = wx - minVal(y) ``` They are also correctly described in Chisel CheatSheet for Chisel 2.2 (with definition...
I believe there is incorrect description of single port memory in Chisel Tutorial 3.0 (beta) Currently it looks like two port memory that can't read and write at the same...