synchronous memory description

[schoeberl]

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I think the synchronous memory description needs some rework. As far as I understand the synchronous memory has changed from Chisel 2 to 3 that the read address is already in a register in the memory module. True? Then it should be mentioned in the tutorial.

This already gives us what we call synchronous read. Why is then in the example another register involved at the output of the synchronous memory? This gives a memory with two cycles latency.

One can always add a register at the output to improve the maximum clock frequency (and FPGA memory blocks have output register in block RAMs that can be used). But I don't think this should be in the tutorial.