Single port RAM in Chisel Tutorial

[bqwer]

I believe there is incorrect description of single port memory in Chisel Tutorial 3.0 (beta) Currently it looks like two port memory that can't read and write at the same time:

val ram1p = Mem(1024, UInt(width = 32))
val reg_raddr = Reg(UInt())
when (wen) { ram1p(waddr) := wdata }
.elsewhen (ren) { reg_raddr := raddr }
val rdata = `ram1p(reg_raddr)

Should be memory with only one address port:

val ram1p = Mem(1024, UInt(width = 32))
val reg_addr = Reg(UInt())
when (wen) { ram1p(addr) := wdata }
.elsewhen (ren) { reg_addr := addr }
val rdata = ram1p(reg_addr)

References: Altera VHDL Examples Xilinx Block Memory Generator User Guide Page 43