[Target][RISCV] Add HwMode support to subregister index size/offset.

[topperc]

This is needed to provide proper size and offset for the GPRPair subreg indices on RISC-V. The size of a GPR already uses HwMode. Previously we said the subreg indices have unknown size and offset, but this stops DwarfExpression::addMachineReg from being able to find the registers that make up the pair.

I believe this fixes https://github.com/llvm/llvm-project/issues/85864 but need to verify.