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zynq-7000 repositories
Zynq_HLS_DDR_Dataflow_kernel_2mm
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This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented with dataflow and DDR3 access with HLS. The Cortex A9 will print...
ZYNQ_Ruler
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Yet Another XC7Z010 Board
libresdr
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Firmware with overclock support for LibreSDR (PlutoSDR clone with Zynq 7020), 27.5 MSPS sample rate over Gigabit Ethernet with libiio/PlutoSDR API