Verilog topic
Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.
zipcpu
A small, light weight, RISC CPU soft core
vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
verilog2factorio
This project will compile verilog (a hardware description language) into factorio blueprints.
OpenROAD
OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/
open-fpga-verilog-tutorial
Learn how to design digital systems and synthesize them into an FPGA using only opensource tools
riscv
RISC-V CPU Core (RV32IM)
apio
:seedling: Open source ecosystem for open FPGA boards