fpga topic

Various HDL (Verilog) IP Cores

ultraembedded

A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog

dpretet

High throughput JPEG decoder in Verilog for FPGA

ultraembedded

A python library for fractional fixed-point (base 2) arithmetic and binary manipulation with Numpy compatibility.

francof2a

Send video/audio over HDMI on an FPGA

hdl-util

Digital logic design tool and simulator

logisim-evolution

open-source IEEE 802.11 WiFi baseband FPGA (chip) design: driver, software

open-sdr

A FPGA friendly 32 bit RISC-V CPU implementation

SpinalHDL

GPGPU microprocessor architecture

jbush001

opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

darklife