chisel3 topic

Wrappers for open source FPU hardware implementations.

jiegec

PYNQ with Chisel and Rust

ekiwi

Chisel library for Unum Type-III Posit Arithmetic

thoughtworks

Yet another toy CPU.

howardlau1999

Based on Chisel3, Rift2Core is a 9-stage, out-of-order, 64-bits RISC-V Core, which supports RV64GC.

whutddk

The Simple 5-staged pipeline RISC-V written in chisel3 for intel FPGA.

panda5mt

Quasar 2.0: Chisel equivalent of SweRV-EL2

Lampro-Mellon

Lectures for the Agile Hardware Design course in Jupyter Notebooks

agile-hw

A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.

Starrynightzyq

Learning how to make RISC-V 32bit CPU with Chisel

rhysd