Marek Materzok

[Sprotty](https://github.com/eclipse-sprotty/sprotty) is a pretty cool diagramming framework, which could be used for dynamic exploring of the transaction graph. Unfortunately, the static graphs we can currently generate have lost some readability...

The current implementation of the instruction cache only services requests when not doing a refill. This introduces unneeded latency: for example, an instruction cache could return the first instruction as...

Use riscv-dv for randomized core testing

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[RISCV-DV](https://github.com/chipsalliance/riscv-dv) is an instruction generator, which can be used for automatic testing of RISC-V cores. For execution, our existing Verilator+cocotb solution can probably be adapted. To verify execution, results should...

Current implementation of loads/stores is a serious bottleneck of the CPU. It has only one RS slot, which means that if the core fetches two load/store instructions close to each...

Change get_result to send_result

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This pull request, inspired by @Arusekk's deliberations, changes the movement of results from FU to announcement from pull-mode (announcement asks units for results) to push-mode (units announce the results themselves)....

Make the processor superscalar

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This issue involves extending the processor so that it can process more than one instruction per cycle. As functional units should naturally scale, the main problem is extending the frontend...

It may be possible to allow condition to be used outside transactions/methods. One way would be to add a dummy method called in each transaction for ensuring mutual exclusivity.

This would be useful for _optimizing_ various units in the core. The script could probably just take the methods exposed by the module and put them on I/O pins. (Question:...

The task is to explore how much calculations can be done in a single FPGA cycle, and create an implementation which minimizes the number of cycles required. In case that...

There exists a benchmark environment which utilizes Embench and LiteX to benchmark various open source cores. Maybe it could be useful to benchmark ours. https://github.com/antmicro/embench-tester