tgingold

I fear that `clkdlybuf4s18_1` (and maybe `clkdlybuf4s18_2`) have a similar issue.

I think the situation has improved recently: most of the signal names are now kept. For `mo`, it is not. The reason is that this signal is not connected. So...

There is no ROM in an fpga, so it is expected that a ROM is mapped to a BRAM. If you RAM is not correctly described as a RAM, the...

I understand the reason of the bug, but I am not sure how to fix it. The result can either be a RAM (with a read port that has a...

Why not but I am not sure you could easily switch the hooks between analysis and synthesis. And I don't think you need it. The first work of the synthesis...

As you can run shell commands from yosys, you could simply do: ``` !ghdl -a --work=xpm xpm_vhdl/src/xpm/xpm_VCOMP.vhd; ghdl --work=work --latches core/hdmi_tx_encoder.vhdl core/types_pkg.vhdl core/vga_to_hdmi.vhdl -e vga_to_hdmi; ```

I do maintain ghdl-yosys-plugin upstream (the original repo), but I don't want to maintain a distribution package. However I suppose this is not a lot of work.

Adding a write_vhdl would be very nice. That's also something I'd like to use and until now I worked around because the priority was not high enough. If you simply...

No, there is currently no support for setting parameters from verilog. You can wrap the vhdl instances into entities without generics.

Well, that's an interesting topic. That was also my initial plan: synthesis records as a group of wires. But that doesn't fly well. Records would become special cases for ports...