sy2002

Additionally to my other test today (https://github.com/sy2002/QNICE-FPGA/issues/87#issuecomment-719979899) one more test: when you press "r" during playing level 2, your player `@` is reset to the starting position, but your old...

There seems to be basic Thread support: https://emscripten.org/docs/porting/pthreads.html

How MMIO devices should behave, e.g. as written [here](https://github.com/sy2002/QNICE-FPGA/blob/develop/vhdl/hw/nexys4ddr/env1.vhd#L438) ``` -- Merge data outputs from all devices into a single data input to the CPU. -- This requires that all...

We must not forget to adjust the assembler and C test programs to adhere to these new semantics and to our new ISR best practices. I adjusted `test_programs/fancy.asm` but all...

We also must not forget to adjust all assembler and C test programs to activate interrupts at first because interrupts are now disabled by default (see https://github.com/sy2002/QNICE-FPGA/issues/139#issuecomment-694474689)

@MJoergen Can you take this one and finalize it? The remaining TODOs as far as I oversee them correctly are: - [x] Hardware: Adjust the **VGA** to the new semantics...

@MJoergen Good point: Macros for the native toolchain's assembler would be nice, so @bernd-ulmann if you added a preprocessor, that would be a nice additional point. But @MJoergen Did you...

Sorry, wrong link in above comment (now edited). You find how to use it in QNICE-FPGA in our README.md, here: https://github.com/sy2002/QNICE-FPGA/tree/dev-int#programming-in-assembler Scroll down to the section *VASM assembler*.

@bernd-ulmann Great idea! And so much simpler and more stable than using a delay. 👍 In the meantime we do have a hardware FIFO in the FPGA UART implementation, so...

@MJoergen Some background about `WAIT_FOR_DATA`: It is an **input** signal of the CPU ([code link](https://github.com/sy2002/QNICE-FPGA/blob/develop/vhdl/qnice_cpu.vhd#L21)) which is adding wait-states when devices need longer than 1/2 of a cycle to deliver...