Angie Wang

Cautionary Tale -- Chisel/ISE issue

3

So I've spent the last n days debugging someone else's Chisel/Verilog, which generally exhibited this symptom: Verilog testbench passes in Vivado (behavioral + post synthesis) Behavioral Verilog testbench passes in...

Changed Vec cloneType

11

Each element's type is properly cloned. See #392

setModuleName is scary... (results in wrong Verilog)

1

Chisel doesn't do a second pass on checking for module name uniqueness if setModuleName is used. I have a parameterizable LUT module that takes in a list of values I...

Clock dividers / multiclock support

5

So... as far as I understand it, not many people have actually played around with multiple clock domains and it only works when clocks are integer multiples of each other......

More Mem questions

2

What is the difference between --backend fpga and --backend v? I was expecting that --backend v would black box the Chisel mems (generated verilog would just have modules + port...

Edit: Nevermind. I guess I was doing something silly. But I'd still like to know what isDebugMem, isInlineMem, and isVCDMem do... Edit2: When isDebugMem is true, write to mem still...

Is there a way to programmatically choose to use/not use an IO?

3

I'm trying to make a very generic counter template, where given a set of user parameters, I'll get back a counter with just the right amount of IO for control...

Hey all, I'm in the process of porting over some Matlab FFT code into Chisel for hardware generation. In Matlab, I've calculated a bunch of constant values that I would...

Peek on internal Vec or elements of Seq?

9

I have an internal signal: `val state = Vec(Reg(init = Bool(true)) +: Seq.fill(p.numBits)(Reg(init = Bool(false))))` In the PeekPokeTester, I try `peek(c.state)` and get ``` [info] - should generate correct control...

VCS Help

1

@jcmartin @donggyukim anyone else -- have you guys run PeekPokeTester w/ the VCS backend? I'm getting a ``` ../vpi.h: In member function 'virtual void vpi_api_t::tick()': ../vpi.h:26: error: 'template class sim_api_t'...