Angie Wang
Angie Wang
Kind of bringing up a topic from the dead, but something like this would be very useful. Ideally, you spec out your particular design's constraints in Chisel and Chisel will...
Yeah, I've already seen both the defaults and what exactly FPGA backend does. I'm just questioning the choice to have isLineMem be false for FPGA backend and true as default....
cloneType should be modified to: override def cloneType: this.type = Vec(elts.map(_.cloneType)).asInstanceOf[this.type] Was running into similar problems earlier (widths of subsequent elements being too small b/c the first element had a...
Do you know if any of the tools have problems handling [-1:0]? I thought they'd error out, but seems like they just trim the signal? Just noticed some of my...
Just noticed this, but I (and at least one other person) ran into similar issues a couple of months ago. I think you should just not make Reg accessible to...
Conditional update is essentially just a DFF reg with input mux. Either you conditionally update to a new value or you pass the output back to the input. (I'm not...
Also, I haven't tried using when instead of Mux, without defining a default case i.e. the feedback. I assume it will derp just like it derps when you don't specify...
At least for me, I definitely typed something like Reg(io.a) expecting it to behave like RegNext(io.a)... I assume that's actually a fairly high frequency mistake. If I did something like...
As a side note, again should probably go in a new issue, but I think the default + might be better off as the current +&. If you wanted to...