firrtl-interpreter
firrtl-interpreter copied to clipboard
freechipsproject
Peek on internal Vec or elements of Seq?
I have an internal signal:
val state = Vec(Reg(init = Bool(true)) +: Seq.fill(p.numBits)(Reg(init = Bool(false))))
In the PeekPokeTester, I try
peek(c.state)
and get
[info] - should generate correct control signals *** FAILED ***
[info] firrtl_interpreter.InterpreterException: Expression key state_0 already in stack
[info] at firrtl_interpreter.ExpressionExecutionStack$$anonfun$push$1.apply(ExpressionExecutionStack.scala:42)
[info] at firrtl_interpreter.ExpressionExecutionStack$$anonfun$push$1.apply(ExpressionExecutionStack.scala:36)
[info] at scala.Option.foreach(Option.scala:257)
[info] at firrtl_interpreter.ExpressionExecutionStack.push(ExpressionExecutionStack.scala:36)
[info] at firrtl_interpreter.LoFirrtlExpressionEvaluator.evaluate(LoFirrtlExpressionEvaluator.scala:273)
[info] at firrtl_interpreter.LoFirrtlExpressionEvaluator$$anonfun$3.apply(LoFirrtlExpressionEvaluator.scala:425)
[info] at firrtl_interpreter.LoFirrtlExpressionEvaluator$$anonfun$3.apply(LoFirrtlExpressionEvaluator.scala:420)
[info] at firrtl_interpreter.Timer.apply(Timer.scala:40)
[info] at firrtl_interpreter.LoFirrtlExpressionEvaluator.firrtl_interpreter$LoFirrtlExpressionEvaluator$$resolveDependency(LoFirrtlExpressionEvaluator.scala:419)
[info] at firrtl_interpreter.LoFirrtlExpressionEvaluator.getValue(LoFirrtlExpressionEvaluator.scala:81)
Some other attempt resulted in
overloaded method value peek with alternatives:
[error] (signal: chisel3.Bits)BigInt <and>
[error] (path: String)BigInt
[error] cannot be applied to (chisel3.core.Vec[chisel3.core.Bool])
[error] peek(c.io.debugStateOneHot.get)
[error] ^
I try c.state.foreach { x => peek(x) } and get the same error.
What I really wanted to do was peek with each state being a Seq instead of a Vec a la:
val state = Reg(init = Bool(true)) +: Seq.fill(p.numBits)(Reg(init = Bool(false)))
with
c.state.foreach { x => peek(x) }
Resulting in:
java.util.NoSuchElementException: key not found: chisel3.core.Bool@25
[info] at scala.collection.MapLike$class.default(MapLike.scala:228)
[info] at scala.collection.AbstractMap.default(Map.scala:59)
[info] at scala.collection.MapLike$class.apply(MapLike.scala:141)
[info] at scala.collection.AbstractMap.apply(Map.scala:59)
[info] at chisel3.iotesters.FirrtlTerpBackend.peek(FirrtlTerpBackend.scala:36)
[info] at chisel3.iotesters.PeekPokeTester.peek(PeekPokeTester.scala:107)
OR
Ideally, I want peek(c.state) to work, where c.state is a Seq.
Ok, seems like I still am not using Vec apply appropriately, resulting in the first issues
[info] firrtl_interpreter.InterpreterException: Expression key state_0 already in stack
I've just been bringing certain signals out via options, but I think this was brought up at some meeting last week (being able to poke internal signals, like in Chisel2; not specific to Seq), and hopefully the testers or whatever will be patched. @chick ?
Re: Seq, idk... basically Seq needs to be treated like a Chisel type, otherwise it sucks to have to use Seq for stuff that Chisel2 Vec used to be ok at (even if used improperly)...
@shunshou I think the basic problem here is that it must be Reg of Vec instead of Vec of Reg. Issue #/chisel3/issues/352 shows an alternative way of representing this. We'd like to flag the wrong construct @ucbjrl are looking into that. If there are other issues about signal access let me know
@chick yeah, I actually went over this with @sdtwigg some weeks ago. It's super confusing!
I'm not sure what @edwardcwang was referring to, but in my latest reply, I was referring more to the ability to peek internal nodes, b/c I don't think it worked a few weeks ago...
That and in general, for the non-homogeneous Vec case, people keep suggesting that I use Seq[T]. The problem with Seq[T] is that there isn't much "Chisel"-y support for Seq's, as compared to when I could use Vec's to perform the same function.
I believe I also tried a few weeks ago, but if I remember correctly, Seq's in Bundles are a huge headache.
@shunshou I think @chick may have been referring to was not using a Vec(Reg(...)) style construct which chisel3 doesn't seem to like. That may account for your firrtl_interpreter.InterpreterException: Expression key state_0 already in stack error.
As for peeking at internal signals, I get the same kind of error as you:
[info] - should baic tests (with firrtl) *** FAILED ***
[info] java.util.NoSuchElementException: key not found: chisel3.core.UInt@33
[info] at scala.collection.MapLike$class.default(MapLike.scala:228)
[info] at scala.collection.AbstractMap.default(Map.scala:59)
[info] at scala.collection.MapLike$class.apply(MapLike.scala:141)
[info] at scala.collection.AbstractMap.apply(Map.scala:59)
[info] at chisel3.iotesters.FirrtlTerpBackend.peek(FirrtlTerpBackend.scala:36)
[info] at chisel3.iotesters.PeekPokeTester$$anonfun$peek$1.apply(PeekPokeTester.scala:151)
[info] at chisel3.iotesters.PeekPokeTester$$anonfun$peek$1.apply(PeekPokeTester.scala:151)
[info] at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
[info] at scala.collection.TraversableLike$$anonfun$map$1.apply(TraversableLike.scala:245)
[info] at scala.collection.Iterator$class.foreach(Iterator.scala:742)
Yea I know what Chick was referring to, and I've already resolved it. It really just needs to be clarified in a manual of some sort why Chisel3 doesn't like it [which Stephen and I talked about in greater detail right after I posted this].
I assume what you want fixed is more just support for peeking internal signals in general.
I care that that's fixed + Chisel support for Seq[T <: Data] is expanded (kind of like Options in Bundles).
When I use peek to get the internal value of a Vec/Array (not in IO bundle),
println(peek(c.srams(0).dataIn.toString))
It will return the following error like yours:
java.util.NoSuchElementException: key not found: UInt<2048>(IO io_dataIn in SRAM)
Have you solved the problem?
