Mohamed Shalan

@donn share with me the timing report(s) to investigate the cause of thes hold vios.

The hold vio is due to a bad constraint for this _input-to-reg_ timing path. To get this fixed we need to adjust the driving cell constraint for input ports; it...

@antonblanchard We can generate the register file. Probably, it will take a week or so before we have it ready.

@antonblanchard I am afraid to say that hierarchical STA does not work anymore as intended due to limitations in the current OpenSTA release. Please don't rely on it as the...

@RTimothyEdwards @antonblanchard The updated `gpio_control_block` was hardened a while back but not pushed. @kareefardi please push it.

Caravel design does not allow top-level cells; hence, top-Level CTS is not possible. However, top-level clock buffering using dedicated buffering macros and/or pass through clocks is undergoing.

Actually, several signals (e.g., `gpio_configure`) are crossing from `SCK` to wb_clk_i w/o passing through synchronizers.

The only way not cause an issue is to stop the CPU and the WB bus when `CSB`is low (active)

@RTimothyEdwards We have been using the `master` branch. Switching to `openframe_development` (as requested by you over the weekend) is not a possibility now. It is behind `master` and there are...

@M0stafaRady