Mohamed Shalan

Migrate to Python3

1

Currently Swift 5.2 is in use. It is better to migrate to Python3.

### Prompt Some generated views (e.g., SDF and SPEF) might be broken due to tool issues. ### Proposal Add a checker to ensure that the generated views look good. For...

Verilog assign and SPEF annotation

4

Does OpenSTA handle assign statements in the netlist while loading SPEF files? Loading a SPEF file to annotate a netlist that has assign statements emits warnings about nets being not...

housekeeping ports are not buffered properly

1

Four output ports are buffered using but_1 cells as they are recognized as Clock Tree leaves. A proper buffering must be established as they drive long nets outside the macro.

housekeeping_spi idata needs a careful attention (Fast to Slow CDC)

2

The `housekeeping_spi` `idata` port is in synch with `wb_clk_i` clock; yet it is written to a register with the `SCK` clock. As the `SCK` clock is slower than `wb_clk_i`, a...

Synchronizers need to be added to prevent any meta-stability because of the asynchronous nature of the input on GPIO pins.

CDC Issues

5

The housekeeping signals: `rdstb`, `wrstb`, `iaddr` and `idata` are crossing from the `SCK` domain to the `wb_clk_i` domain w/o any synchronizers. They must be synchronized w/ the `wb_clk_i` clock to...

GF180 512x8 SRAM Macro Verilog model has 1.8V timing parameters

7

This might be the case for other SRAM macros. 5.0V timing parameters should be used instead as Caravel runs @ a single 5.0v supply.