anasymod
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sgherbst
A framework for FPGA emulation of mixed-signal systems
At the moment, the minimum timestep is computed as min(min(min(a, b), c), d) rather than min(min(a, b), min(c, d)). We thought that the synthesis tool would automatically optimize this, but...
Since it can take a long time to build bit files, **anasymod** should make it harder to accidentally delete them (the initial cleanup process removes the old bitfile, so if...
The error now is quite low-level, so it would be nice to provide a more descriptive error message & tips for the user to resolve this issue (add a directory...
It's been a long time since the readme was updated; many things have changed and new capabilities have been added.
This largely depends on #23, since Ultra96 is a board that requires the PL clock to be sourced from the PS. Actually, ``ULTRA96`` is already a board type, but it...
Some FPGA boards (e.g., Ultra96 and TE0720) do not provide a clock directly from the PCB to the programmable logic (PL). Instead, they provide a clock to the programmable subsystem...
Some of the key areas with low coverage are: * Exercising the command-line mode (have to figure out a good way to do this while gathering coverage information) * ``add_sources``...
This could be accomplished by compiling a simple logical function to an EDIF format, which would then be included in the build sources. I think this would likely require post-synthesis...
Currently, most tests in the regression suite are run using simulation only; just a couple are run on a real FPGA board. It would be good to schedule a more...
Recently functions such as ``sleep`` and ``stall`` have been added to the emulator controller, but we don't yet have regression tests to exercise these functions on a real FPGA board.