Schuyler Eldridge

Width inference should relegate this to a FIRRTL-time check, yes? Changing FIRRTL semantics to be strict seems to make sense to me. Similarly, enabling a new check that runs by...

Note: that because options are just a means to generate `Annotation`s, it's really the `Annotation`s that are controlling this in any stage/phase/transform downstream of when the `Annotation` was created. We...

I don't like the argument of `forall` or `exists` being the reason why this should work. My concern is that this is a "reduction" and reductions (Scala's `reduce` or Haskell's...

You can coerce this now if you are comfortable with the type of the Bundle being an inferred-width `UInt`. This obviously loses the type safety in the bundle declaration, but...

Mid-term we need to capture user-defined Chisel types in FIRRTL IR. (We are already running into a need for this now that aggregate preservation is coming online with CIRCT and...

Another example to think about is how does this work for parameters that should be represented in-IR. This is relatively straightforward to start with for external modules because they already...

> These are parameters that are specific to how a thing is used, not really a property of the thing itself. The "how a thing is used", in Chisel at...

Alternatively, if it's a list of keywords to avoid you can use the parent of the Verilog rename transform. (Which would mangle internal signal names, too.) **Edit: `RemoveKeywordCollisions`**

Note that for `[A]`, what is actually going on is that `withReset` has no effect on a `Definition`. `withReset` creates a node cast to async reset. `Definition`s doesn't actually create...

> The weirdness in A is just a bug, this is a known issue (although looks like I never filed it), that Chisel defaults to Bool for the top module...