Schuyler Eldridge

#2038 should fix this. The above input will now generate: ```verilog module Foo( input a, input [12:0] inp_6, output [13:0] tmp13 ); wire [13:0] _GEN_0 = inp_6 + 13'h1; assign...

I believe that the support that you're looking for is already in place with the `--wi`, `--wo`, and `--wio`. These will turn on unconnected IO warnings for inputs, outputs, or...

One approach is to use [coursier](https://github.com/coursier/coursier) to grab a binary. Once you have the coursier command line tool, you have two options. You can download diagrammer and all its dependencies...

This was never actually clear to me and I would need to read some code and/or do some experiments to figure out what is going on here. My original understanding...

__Edit: @mithro beat me by a few minutes! Original reply with more detail on FIRRTL below.__ Are you aware of [FIRRTL](https://GitHub.com/freechipsproject/FIRRTL)? Chisel3 already compiles to FIRRTL (a flexible intermediate representation...

@Nic30: good points. - Python/C/C++/MyLanguage libraries for FIRRTL seems to make sense to improve the ease of frontend/backend development. The existing antlr and protobuf specifications for FIRRTL may already ease...

@dvc94ch, @Nic30: FIRRTL supports arbitrary numbers of clocks and, consequently, you can use FIRRTL IR to write circuits with multiple clock domains. You may have been thinking of the default...

#### Blackbox Escape Hatch The robust blackbox support in Chisel and backed by FIRRTL `ExtModule` acts as an escape hatch for almost everything stemming from, "I can do this in...

@Dolu1990: thanks for the feedback and thoughts! - Yeah, __BB/Async__: this is the temporary solution. A more robust one is in the works. An RFC or discussion on the tracking...

Yeah, this is wrong. This is one area where the FIRRTL spec actually has a lot of clarifying information on how this is supposed to work (which is admittedly based...