Schuyler Eldridge

As @rwy7 has pointed out, the issue here is that the external module does not have a layer enables (and it can't as we haven't defined this). So, therefore this...

Discussed offline with @dtzSiFive. There appears to be at least one register canonicalizer (see `foldHiddenReset` in `FIRRTLFolds.cpp`) and this shouldn't be run _before_ `RandomizeRegisterInit` because that can cause changes in...

This is getting pretty Verilog-specific which I don't really like. Specifically, in order for this to work, it likely also needs an `fopen`/`fclose` which returns an ID and that is...

> The reason of post processing is hard is we also want write a giant log into file while keeping stdout clean for other usages e.g. uart. Thinking about this......

If we _did_ do this, then it's reasonable to both build the logging library in Chisel and provide the script for working with this in Chisel as well. 🤓

Err... I'm saying that I'm not convinced of the need for the file descriptor and think the logging can be packaged up with a library in Chisel and a script...

Going off of what I was suggesting above... Something like the following may make more sense: ``` firrtl circuit Foo: file Bar, "Bar.log", read public module Foo: input clock: Clock...

There's a couple of other things that need to be considered here: 1. Mangling of private modules (private symbols). If the two circuits both have a `module Queue`, then these...

I'm not super worried about accidental name collisions as this flow should theoretically allow for that to always be resolved so long as two circuits are linked. The only time...

> Is it necessary to support .fir files as input? The FIRRTL parser has a bunch of options which I personally think should be processed in firtool rather than firld....