open-register-design-tool
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sdnellen
Tool to generate register RTL, models, and docs using SystemRDL or JSpec input
Hi Scott, Looks like when we define a `read to clear` register, it's defaulting to `sw_precedence`. These registers should rather default to `hw_precedence`. Thanks and keep up the awesome work!...
Hi, Thanks for your work on ORDT. It is very impressive and usefull tool. I'm trying to define holding registers in RDL, and I'm not sure how to do that....
I've been trying to run the https://github.com/SystemRDL/RALBot-html/blob/master/example/turboencabulator.rdl example to see if I can get Ordt to parse the same file. As it appears, Ordt fails to parse the example because...
From open-register-design-tool created by [WebMonkey007](https://github.com/WebMonkey007): Juniper/open-register-design-tool#52 The current XML output includes the Instance view but does not include the "data dictionary " ie addrmap counters { counter_t transaction_cnt[10]; counter_t error_cnt[5];...
Gradle task that copies MyDebugController.example to MyDebugController.java fails in windows 10 for a newly cloned repo. As workaround, just copy manually to create the file.
antlr 4.7.2 compile of grammar files fails - seems to be issue with escape dquote fragment. For now staying with 4.5.3 which works, but would be good to move to...
From open-register-design-tool created by [neenuprince](https://github.com/neenuprince): Juniper/open-register-design-tool#70 The .jrdl_logic.sv file generates a signal for the HW Read SW write register, that is floating. the signal l2d__r is the signal that remains...
From open-register-design-tool created by [sjalloq](https://github.com/sjalloq): Juniper/open-register-design-tool#68 I had a quick look in the closed issues but couldn't see a matching title so forgive me if this has been reported already....
From open-register-design-tool created by [sjalloq](https://github.com/sjalloq): Juniper/open-register-design-tool#63 Just checked out HEAD and tried to run ./gradlew but get a build error. Seems to be a broken path to shadow.jar on github....
From open-register-design-tool created by [petenixon](https://github.com/petenixon): Juniper/open-register-design-tool#62 Hi @sdnellen, It looks like issue #59 is still a problem, due to various downstream physical design, gate-level simulation, and DFT issues. Please see...