Martin Schoeberl

mv fifo over from ip-contributions

2

### Contributor Checklist - [x] Did you add Scaladoc to every public function/method? - [x] Did you add at least one test demonstrating the PR? - [ ] Did you...

stdlib: add UART from ip-contributions

11

### Contributor Checklist - [ ] Did you add Scaladoc to every public function/method? - [*] Did you add at least one test demonstrating the PR? - [*] Did you...

Add a ReadyValidIO factory, fixes #1350

2

### Contributor Checklist - [y] Did you add Scaladoc to every public function/method? - [y] Did you add at least one test demonstrating the PR? - [y] Did you delete...

sub field assignment

1

As I cannot reopen issue #878, I created a new one. If this is too hard to implement then we can close it again (maybe with an argument). Subword (individual...

Remove implicit width truncation / Don't repeat Verilog's assignment issue in Chisel

49

I just realized that assignment of a larger width signal to a small width signal results in a silent truncation in Chisel. This is one of the worst issues in...

incrementing a register

1

**Type of issue**: feature request **Impact**: API addition (no impact on existing code) **Development Phase**: proposal Incrementing a register (a counter) is such a common operation. Maybe we should support...

We should at the bare minimum have the titles and authors of presentations listed. Any conference/workshop has this. Then add the additional information, if available. We did not do all...

Minor additions: step and joinAll

9

Two small additions would be nice: ``` dut.clock.step() ``` is a bit long to type, just a ```step()``` would be nice and short. A function to join all parallel threads,...

I think the synchronous memory description needs some rework. As far as I understand the synchronous memory has changed from Chisel 2 to 3 that the read address is already...

Register size inference

12

The following code should size a register for 4 bits by using an UInt constant: val reg = Reg(UInt(15)) reg := reg + UInt(1) io.result := reg However, the resulting...