Ronny Nilsson

I have found that vunit don't build full dependency between verilog and vhdl #929. I have updated project.py to also check if a instance is a VHDL-instance. I have also...

I have a run.py in top-directory that scans sub-directories for testbenches. The testbenches are written in Systemverilog. The DUTs are either VHDL or Systemverilog containing mixed VHDL and Systemverilog submodules....