Dependecies for Systemverilog and mixed designs

[roynil]

I have a run.py in top-directory that scans sub-directories for testbenches. The testbenches are written in Systemverilog. The DUTs are either VHDL or Systemverilog containing mixed VHDL and Systemverilog submodules.

If do python run.py lib.some_tb.some_test everything compiles and run perfectly. But if I try python -m lib.some_tb.some_test then only the Systemverilog testbench and the immediate Systemverilog DUT compiles. For example instantiated interfaces are not compiled.

If I do a get_implementation_subset on the Systemverilog tb-file the interface file is not included. Neither any VHDL-submodule.

Small example: vtest.tar.gz