Rose Thompson
Rose Thompson
Return key on the same cycle as write to save one cycle of latency. Check if this increases the critical path. ``` // On a write, set the valid bit...
Each memory access in a HPTWalk needs to be potentially flushed if the PMA/P checkers generate an access fault. Specially the store on UDPATE_PTE needs to check for access violation....
Misaligned faults may be asserted when a TLB miss occurs. Because Wally only implements misaligned support for cacheable memory, the address must be translated before cacheablity is known. Table 15...
Think through the purpose of IgnoreRequest in the IFU and LSU. It is unused in the IFU and only use by atomic in the LSU. IgnorerRequestTLB is generated by the...
PBMT configured misaligned addresses do not agree between ImperasDV and Wally. wsim rv64gc tests/coverage/tlbMisaligned.elf --lockstep ``` Info (IDV) Instruction executed prior to mismatch '0x8001503c(main+3c): 929e add x5,x5,x7' # Error (IDV)...
With the removal of SDIO the existing SD Card model no longer works. Need to switch to SPI.
I believe I found a bug in OpenSBI version 1.6 used in buildroot tag 2024.11.x with kernel 6.12.8. OpenSBI makes two calls to fdt_open_into increasing the length of the device...
Similar to Issue #1263, misaligned instruction page faults do not set the correct xtval. I have a proposed fix, but it adds 3 XLEN registers to pipeline PCSpillF to the...
Lockstep does not detect all types of failures. The current WALLY-COV-fsh.S functional coverage test causes a trap without a trap handler. ImperasDV and Wally both inter an infinite loop of...
I believe there is a bug in the fifo by code inspection and FPGA debugging. It appears possible to stall a load of the RXDATA register and potentially read out...