openhwgroup
Misalgined Instruction Pagefault Crossing Virtual pages Bug
Similar to Issue #1263, misaligned instruction page faults do not set the correct xtval. I have a proposed fix, but it adds 3 XLEN registers to pipeline PCSpillF to the Memory stage. I also wrote a regression test to drive Wally into this state; however, I am having difficulty getting the program to terminate gracefully after the exception. It will likely require a special trap handler different from the other coverage tests. The test attempts to execute an instruction from a page with an invalid PTE. The trap handler needs to jump somewhere other than the next instruction or it needs to update the PTE with a valid entry.
Shouldn’t a page fault on a page with an invalid PTE just terminate the process?
On May 7, 2025, at 4:50 PM, Rose Thompson @.***> wrote:
rosethompson created an issue (openhwgroup/cvw#1406) https://github.com/openhwgroup/cvw/issues/1406 Similar to Issue #1263 https://github.com/openhwgroup/cvw/issues/1263, misaligned instruction page faults do not set the correct xtval. I have a proposed fix, but it adds 3 XLEN registers to pipeline PCSpillF to the Memory stage. I also wrote a regression test to drive Wally into this state; however, I am having difficulty getting the program to terminate gracefully after the exception. It will likely require a special trap handler different from the other coverage tests. The test attempts to execute an instruction from a page with an invalid PTE. The trap handler needs to jump somewhere other than the next instruction or it needs to update the PTE with a valid entry.
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