riscv-ctg
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riscv-software-src
Additional coverpoints/scenarios for FP extensions: - In RISC-V, the same register is used for storing both the single and double precision numbers. The single precision numbers are NaN boxed when...
## Summary Coverpoints spanning across multiple instructions help identify interesting instruction sequences which have architectural significance such as structural hazards and data hazards. CTG lacks the infrastructure necessary to generate...
Task : Explicitly specify redundant coverpoints in the terminal messages - The normalization functions used to abstract representations of coverpoints can potentially produce duplicate coverpoints. It is desirable to identify...
Hi, Based on the discussion I have modified the sigupd_f macro. And the definition of the SREG and LREG will get changed based on the each F test. The macro...
- Remove already assigned registers using `op_vars` while assigning testreg and swreg.
The purpose of this PR is to add the coverpoints for the PMP, Privileged architecture following the Test Plan available [here](https://docs.google.com/spreadsheets/d/1p13gic7BD6aq7n_dHrqti4QmlGpxY7FkF17RVbG4DC0/edit#gid=0) Please review the the coverage report that is available...
This patch introduces the RISC-V Zfa extension, which introduces additional floating-point extensions: * fli (load-immediate) with pre-defined immediates * fminm/fmaxm (like fmin/fmax but with different NaN behaviour) * fround/froundmx (round...
**Added Support for Zfh and Zfinx extensions** This PR adds - Added cover group format for RV32Zfh instructions. - Added cover group format for RV64Zfh instructions. - Added cover group...
The variable 'xlenlim' referenced in the abstract combination of a few bitmanip instructions within the configuration files rv32i_b.cgf, rv32e_b.cgf, and rv64i_b.cgf appears to be "not defined", leading to an error....
