Necessary corner cases and tests for `FD` extensions.

[pawks]

Additional coverpoints/scenarios for FP extensions:

• In RISC-V, the same register is used for storing both the single and double precision numbers. The single precision numbers are NaN boxed when stored in a 64 bit wide register. In such a configuration, if the source to a sp operation is incorrectly NaN boxed, the input should be a canonical NaN. This can be tested by a fld -> sp op -> fsw sequence. Capturing coverage for this requires further thought.
• Certain operations propagate the NaN payloads, but the arithmetic operations canonicalize. In case a NaN boxed sp value is stored using a dp store operation, the nan payload should be identical. Similar argument can also be made for a flw -> fsjn* -> fsd sequence.

Both the aforementioned scenarios are also applicable for the mv operations to/from the integer register file.

[allenjbaum]

Note that Z<h,f,d>inx operations do not Nan box!

On Sun, Mar 27, 2022 at 9:53 PM S Pawan Kumar @.***> wrote:

Additional coverpoints/scenarios for FP extensions:

• In RISC-V, the same register is used for storing both the single and double precision numbers. The single precision numbers are NaN boxed when stored in a 64 bit wide register. In such a configuration, if the source to a sp operation is incorrectly NaN boxed, the input should be a canonical NaN. This can be tested by a fld -> sp op -> fsw sequence. Capturing coverage for this requires further thought.
• Certain operations propagate the NaN payloads, but the arithmetic operations canonicalize. In case a NaN boxed sp value is stored using a dp store operation, the nan payload should be identical. Similar argument can also be made for a flw -> fsjn* -> fsd sequence.

Both the aforementioned scenarios are also applicable for the mv operations to/from the integer register file.

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