riscv-ctg
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riscv-software-src
Add support for Zfinx and Zfh extension
Added Support for Zfh and Zfinx extensions
This PR adds
- Added cover group format for RV32Zfh instructions.
- Added cover group format for RV64Zfh instructions.
- Added cover group format for RV64Zfinx instructions.
- Introduced half width and half word in Nan boxing functionality to accommodate Zfh extensions.
- Introduced two new flags (ZFINX and ZDINX) to aid the compilation of floating ops into integer regs.
@neelgala , -Please have your review and let us know if more information would help.
@neelgala , -Please have your review and let us know if more information would help.
I'm not familiar enough with CTG to do a good job of reviewing this (though more comments would help a lot. If you've run this under riscof, and it passes tests with the correct coverage, for RV64 and RV32, with & without D/Dinx configuration, then that's the major thing. Defining coverage is what I want to see, and these extensions have more corner cases to watch out for, especially register assignments, nan-Boxing, etc.
Hmm - I'm not sure we should still be referring to incoresemi license details for any of tese; that somehow seems wrong (As opposed to the icense terms that most other repos use)
After some digging, I found this pr, and seems some of the ctg files need changes on check ISA, like in rv32h_fdiv.cgf#L5
- check ISA:=regex(.*I.*F.*)
Should be
- check ISA:=regex(.*I.*F.*Zfh.*)
The related issues are: https://github.com/riscv-non-isa/riscv-arch-test/issues/453 https://github.com/riscv-non-isa/riscv-arch-test/issues/448
Maybe some changes are needed?
@anuani21, I have made a commit to resolve the conflicts and to enable the CI. It seems like CI is failing, please take a look at it.
Ok, I will check and let you know
On Thu, 18 Jul, 2024, 3:23 pm Umer Shahid, @.***> wrote:
@anuani21 https://github.com/anuani21, I have made a commit to resolve the conflicts and to enable the CI. It seems like CI is failing, please take a look at it.
— Reply to this email directly, view it on GitHub https://github.com/riscv-software-src/riscv-ctg/pull/67#issuecomment-2236098395, or unsubscribe https://github.com/notifications/unsubscribe-auth/A3G6FFZYP4N454USVGZQ5STZM6GBNAVCNFSM6AAAAAAZ4AJ6ISVHI2DSMVQWIX3LMV43OSLTON2WKQ3PNVWWK3TUHMZDEMZWGA4TQMZZGU . You are receiving this because you were mentioned.Message ID: @.***>
@anuani21 CI is still failing. I think there is some issue in test generation for rv32 type tests.