rbrglez

Results 7 comments of rbrglez

Question: Cache Synthesis Results of Xilinx IP

Could someone provide an example of caching IPs with generator? If this is possible it would speed up our build times significantly

[Documentation] - Unable to Reproduce Minimal Test from README Instructions

I see that the same issue was raised here: #379 Resolution was, that `README.md`should be changed

Synchronizing core and git repository version

Yes, this behavior already exists in fusesoc. Example of check-outing same library with fusesoc, but with different versions: ```bash fusesoc library add open-logic-3.0.0 https://github.com/open-logic/open-logic --sync-version 3.0.0 fusesoc library add open-logic-3.1.0...

Vivado: used_in_implementation property not supported for .vhd/.v files with simulation tag

I've experimented a bit with the `USED_IN` and `USED_IN_IMPLEMENTATION` properties in Vivado 2023.2. To exclude VHDL files from the implementation flow, you should use the `USED_IN` property, not `USED_IN_IMPLEMENTATION`. How...

Question: execute command before generating a project using Vivado

Did you try to use generators instead of hooks? https://fusesoc.readthedocs.io/en/stable/user/build_system/generators.html# If you can provide a minimal example project with PeakHDL I can help you configure fusesoc generators.

Question: execute command before generating a project using Vivado

Using this [repository](https://github.com/fusesoc/fusesoc-generators/tree/master) I was able to get generators working in FuseSoC. At work, I'm now using them to generate registers.

Question: execute command before generating a project using Vivado

I have created a fork of the FuseSoC generator repository and added a new generator that produces the current date. You can view the fork here: https://github.com/rbrglez/fusesoc-generators/tree/feature/date Additionally, I included...