Vivado: used_in_implementation property not supported for .vhd/.v files with simulation tag

[rbrglez]

Description:

When using the simulation tag on testbench files in Vivado via FuseSoc + Edalize, Vivado fails to open the design. This is because the tool attempts to set the used_in_implementation property on VHDL and Verilog source files, which is not supported.

Error message from Vivado:

ERROR: [Common 17-54] The object 'file' does not have a property 'used_in_implementation'.

Reproduction:

Here is an excerpt from the core file I used to test this behavior:

################################################################################
# Filesets
################################################################################
filesets:
  rtl_files:
    depend:
      - "^open-logic:open-logic-aviat:base:4.0.0"

    files:
      - "rtl/bucket.vhd"
      - "rtl/checkpoint.vhd"
      - "rtl/leaky_bucket.vhd"
    file_type: "vhdlSource-2008"

  tb_files:
    files:
      - "tb/bucket_tb.vhd"
      - "tb/checkpoint_tb.vhd"
      - "tb/leaky_bucket_tb.vhd"
    file_type: "vhdlSource-2008"
    tags:
      - "simulation"

Offending code in Edalize (Tool Vivado backend):

https://github.com/olofk/edalize/blob/6f3260c67331bd300443014b024219214337da82/edalize/tools/vivado.py#L155-L157

The same issue is also present in Flow Vivado backend, but unfortunately I didn't find the offending code.

Proposed solution:

Skip setting used_in_implementation if the file type is a source file (vhdlSource, verilogSource, etc.). These properties are not valid for HDL files in Vivado and will generate an error.

[olofk]

Hmm... did Vivado drop this property? It looks like it should still be supported https://docs.amd.com/r/en-US/ug912-vivado-properties/USED_IN and that it should work for vhdl/verilog files. Could you try if the USED_IN property works, i.e. changing used_in_implementation to USED_IN implementation. Or perhaps it just needs to be uppercase.

[rbrglez]

I've experimented a bit with the USED_IN and USED_IN_IMPLEMENTATION properties in Vivado 2023.2.

To exclude VHDL files from the implementation flow, you should use the USED_IN property, not USED_IN_IMPLEMENTATION.

How USED_IN Works:

The USED_IN property explicitly defines which design flows a file is used in. When you set it, only the specified values (e.g., synthesis, simulation, etc.) are enabled. All other flows are implicitly disabled.

This works as expected:

set_property USED_IN {simulation synthesis} [get_files *.vhd]

This doesn't work:

set_property used_in_implementation false [get_files *.vhd]

Note: Property names in Vivado Tcl are case-insensitive. For example, USED_IN and used_in are treated the same. Using uppercase or lowercase has no impact on functionality.