Question: Cache Synthesis Results of Xilinx IP

[maximiliankir]

I have a project which uses the Xilinx DDR4 MIG. I build the project with fusesoc and synthesize with Vivado. The DDR4 MIG is generated with a tcl script, which is called by fusesoc.

The problem is, that the synthesis of the DDR4 MIG takes some time and is executed before the synthesis of my SystemVerilog code. So I have to wait for the IP synthesis to finish everytime before finding some error in my code, because the Vivado project is regenerated everytime.

Is it somehow possible to cache the synthesis results of the IP, when it is unchanged? This would save me a lot of time.

[olofk]

If possible, I would suggest looking at implementing this with a generator. That allows you to cache it.

[maximiliankir]

I'm not quite sure, if this is what I am looking for. My tcl sript doesn't generate Verilog Code, it adds an IP to the Vivado project:

set ipName xlnx_mig_ddr4
create_ip -name ddr4 -vendor xilinx.com -library ip -version 2.2 -module_name $ipName

set_property -dict [list CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram_062} \
                           CONFIG.C0.DDR4_TimePeriod {833} \
                           CONFIG.C0.DDR4_InputClockPeriod {3332} \
                           CONFIG.C0.DDR4_CLKOUT0_DIVIDE {5} \
                           CONFIG.C0.DDR4_MemoryPart {MT40A256M16LY-062E} \
                           CONFIG.C0.DDR4_DataWidth {16} \
                           CONFIG.C0.DDR4_CasWriteLatency {12} \
                           CONFIG.C0.DDR4_AxiDataWidth {128} \
                           CONFIG.C0.DDR4_AxiAddressWidth {29} \
                           CONFIG.C0.DDR4_AxiIDWidth {8} \
                           CONFIG.ADDN_UI_CLKOUT1_FREQ_HZ {100} \
                           CONFIG.System_Clock {No_Buffer} \
                           CONFIG.Reference_Clock {No_Buffer} \
                           CONFIG.C0.BANK_GROUP_WIDTH {1} \
                           CONFIG.C0.DDR4_AxiSelection {true} \
                     ] [get_ips $ipName]

From what I read, I don't think that the generator feature would help here, because the Vivado project would still be regenerated and Vivado needs to synthesize the IP everytime. But maybe I am wrong. Do you know an example, where parts of a Vivado project are cached?

[rbrglez]

Could someone provide an example of caching IPs with generator? If this is possible it would speed up our build times significantly

[ArkoshEternal]

You can also just use no-export and use a user-managed IP through vivado if you're able to check it in to your repo. We have that since we have modifications to the IP customization and it works quite well for our issues.

You could have this as a generator where you have the instructions to run the out of context run and then scoop all of the output code, and implement caching on an input basis, but that is a lot of backend scripting to ensure that you are getting all of the build dependencies out since it does not neatly go into a parseable list and modifications to the IP block can cause drastic differences in the output product..